Wishbone Bus#

Implements the register block using a Wishbone B4 CPU interface.

The wishbone interface comes in two i/o port flavors:

SystemVerilog Interface

Command line: --cpuif wishbone
Interface Definition: wishbone_intf.sv
Class: peakrdl_regblock.cpuif.wishbone.Wishbone_Cpuif

Flattened inputs/outputs

Flattens the interface into discrete input and output ports.

Command line: --cpuif wishbone-flat
Class: peakrdl_regblock.cpuif.wishbone.Wishbone_Cpuif_flattened

Implementation Details#

This implementation of the Wishbone protocol has the following features: - Classic Wishbone Operations (SINGLE_READ and SINGLE_WRITE) - Stall and Error optional output signals

Note that the cyc signal is not connected and it is a placeholder, since it is redundant in wishbone classic operations. Commands are captured based on stb.

Wishbone Bus

Contents

Wishbone Bus#

Implementation Details#