Introduction#
PeakRDL-regblock is a free and open-source control & status register (CSR) compiler. This code generator translates your SystemRDL register description into a synthesizable SystemVerilog RTL module that can be easily instantiated into your hardware design.
Generates fully synthesizable SystemVerilog RTL (IEEE 1800-2012)
Options for many popular CPU interface protocols (AMBA APB, AXI4-Lite, and more)
Configurable pipelining options for designs with fast clock rates.
Broad support for SystemRDL 2.0 features
Quick Start#
The easiest way to use PeakRDL-regblock is via the PeakRDL command line tool:
# Install PeakRDL-regblock along with the command-line tool
python3 -m pip install peakrdl-regblock[cli]
# Export!
peakrdl regblock atxmega_spi.rdl -o regblock/ --cpuif axi4-lite
Looking for VHDL?#
This project generates SystemVerilog RTL. If you prefer using VHDL, check out the sister project which aims to be a feature-equivalent fork of PeakRDL-regblock: PeakRDL-regblock-VHDL