Exporter API

If you are not using the PeakRDL command-line tool, you can still generate regblocks programmaticaly using the exporter API:

class peakrdl_regblock.RegblockExporter(**kwargs: Any)
export(node: RootNode | AddrmapNode, output_dir: str, **kwargs: Any) → None
Parameters:

  • node (AddrmapNode) – Top-level SystemRDL node to export.

  • output_dir (str) – Path to the output directory where generated SystemVerilog will be written. Output includes two files: a module definition and package definition.

  • cpuif_cls (peakrdl_regblock.cpuif.CpuifBase) – Specify the class type that implements the CPU interface of your choice. Defaults to AMBA APB4.

  • module_name (str) – Override the SystemVerilog module name. By default, the module name is the top-level node’s name.

  • package_name (str) – Override the SystemVerilog package name. By default, the package name is the top-level node’s name with a “_pkg” suffix.

  • reuse_hwif_typedefs (bool) –

    By default, the exporter will attempt to re-use hwif struct definitions for nodes that are equivalent. This allows for better modularity and type reuse. Struct type names are derived using the SystemRDL component’s type name and declared lexical scope path.

    If this is not desireable, override this parameter to False and structs will be generated more naively using their hierarchical paths.

  • retime_read_fanin (bool) –

    Set this to True to enable additional read path retiming. For large register blocks that operate at demanding clock rates, this may be necessary in order to manage large readback fan-in.

    The retiming flop stage is automatically placed in the most optimal point in the readback path so that logic-levels and fanin are minimized.

    Enabling this option will increase read transfer latency by 1 clock cycle.

  • retime_read_response (bool) –

    Set this to True to enable an additional retiming flop stage between the readback mux and the CPU interface response logic. This option may be beneficial for some CPU interfaces that implement the response logic fully combinationally. Enabling this stage can better isolate timing paths in the register file from the rest of your system.

    Enabling this when using CPU interfaces that already implement the response path sequentially may not result in any meaningful timing improvement.

    Enabling this option will increase read transfer latency by 1 clock cycle.

  • retime_external_reg (bool) – Retime outputs to external reg components.

  • retime_external_regfile (bool) – Retime outputs to external regfile components.

  • retime_external_mem (bool) – Retime outputs to external mem components.

  • retime_external_addrmap (bool) – Retime outputs to external addrmap components.

  • generate_hwif_report (bool) – If set, generates a hwif report that can help designers understand the contents of the hwif_in and hwif_out structures.

  • address_width (int) – Override the CPU interface’s address width. By default, address width is sized to the contents of the regblock.

  • default_reset_activelow (bool) – If overriden to True, default reset is active-low instead of active-high.

  • default_reset_async (bool) – If overriden to True, default reset is asynchronous instead of synchronous.

Example

Below is a simple example that demonstrates how to generate a SystemVerilog implementation from SystemRDL source.

from systemrdl import RDLCompiler, RDLCompileError
from peakrdl_regblock import RegblockExporter
from peakrdl_regblock.cpuif.axi4lite import AXI4Lite_Cpuif
from peakrdl_regblock.udps import ALL_UDPS

input_files = [
    "PATH/TO/my_register_block.rdl"
]

# Create an instance of the compiler
rdlc = RDLCompiler()

# Register all UDPs that 'regblock' requires
for udp in ALL_UDPS:
    rdlc.register_udp(udp)

try:
    # Compile your RDL files
    for input_file in input_files:
        rdlc.compile_file(input_file)

    # Elaborate the design
    root = rdlc.elaborate()
except RDLCompileError:
    # A compilation error occurred. Exit with error code
    sys.exit(1)

# Export a SystemVerilog implementation
exporter = RegblockExporter()
exporter.export(
    root, "path/to/output_dir",
    cpuif_cls=AXI4Lite_Cpuif
)