Intel Avalon

Implements the register block using an Intel Avalon MM CPU interface.

The Avalon interface comes in two i/o port flavors:

SystemVerilog Interface

• Command line: --cpuif avalon-mm

• Interface Definition: avalon_mm_intf.sv

• Class: peakrdl_regblock.cpuif.avalon.Avalon_Cpuif

Flattened inputs/outputs

Flattens the interface into discrete input and output ports.

• Command line: --cpuif avalon-mm-flat

• Class: peakrdl_regblock.cpuif.avalon.Avalon_Cpuif_flattened

Implementation Details

This implementation of the Avalon protocol has the following features:

• Interface uses word addressing.

• Supports pipelined transfers

• Responses may have variable latency

  In most cases, latency is fixed and is determined by how many retiming stages are enabled in your design. However if your design contains external components, access latency is not guaranteed to be uniform.