PeakRDL-regblock is a free and open-source control & status register (CSR) compiler. This code generator translates your SystemRDL register description into a synthesizable SystemVerilog RTL module that can be easily instantiated into your hardware design.
Generates fully synthesizable SystemVerilog RTL (IEEE 1800-2012)
Options for many popular CPU interface protocols (AMBA APB, AXI4-Lite, and more)
Configurable pipelining options for designs with fast clock rates.
Broad support for SystemRDL 2.0 features
Fully synthesizable SystemVerilog. Tested on Xilinx/AMD’s Vivado & Intel Quartus
The PeakRDL-regblock SV generator is still in pre-production (v0.x version numbers). During this time, I may decide to refactor things which could break compatibility.
Install from PyPi using pip
python3 -m pip install peakrdl-regblock
Below is a simple example that demonstrates how to generate a SystemVerilog implementation from SystemRDL source.
from systemrdl import RDLCompiler, RDLCompileError from peakrdl_regblock import RegblockExporter from peakrdl_regblock.cpuif.apb3 import APB3_Cpuif input_files = [ "PATH/TO/my_register_block.rdl" ] # Create an instance of the compiler rdlc = RDLCompiler() try: # Compile your RDL files for input_file in input_files: rdlc.compile_file(input_file) # Elaborate the design root = rdlc.elaborate() except RDLCompileError: # A compilation error occurred. Exit with error code sys.exit(1) # Export a SystemVerilog implementation exporter = RegblockExporter() exporter.export( root, "path/to/output_dir", cpuif_cls=APB3_Cpuif )